Electrically erasable programmable nonvolatile memories include a flash memory as well known in the art, which comprises a cell array of NAND-connected or NOR-connected memory cells having a floating gate structure. A ferroelectric memory is also known as a nonvolatile fast random access memory.
On the other hand, technologies of pattering memory cells much finer include a resistance variable memory, which uses a variable resistive element in a memory cell as proposed. Known examples of the variable resistive element include a phase change memory device that varies the resistance in accordance with the variation in crystal/amorphous states of a chalcogenide compound; an MRAM device that uses a variation in resistance due to the tunnel magneto-resistance effect; a polymer ferroelectric RANI (PFRAM) memory device including resistive elements formed of a conductive polymer; and a ReRAM device that causes a variation in resistance on electrical pulse application (Patent Document 1).
The resistance variable memory may configure a memory cell with a serial circuit of a Schottky diode and a resistance variable element in place of the transistor. Accordingly, it can be stacked easier and three-dimensionally structured to achieve much higher integration as an advantage (Patent Document 2).
When data write/erase to the memory cell changes the state of the variable resistive element, the variable resistive element and the non-ohmic element produce heat. Therefore, simultaneous data write/erase to a number of memory cells exerts a larger influence by the heat production and in turn results in the loss of data stability. This problem is further actualized by higher integration of the nonvolatile memory.
[Patent Document 1]
JP 2006-344349A, paragraph 0021
[Patent Document 2]
JP 2005-522045A